Granted Patent
Utility
US 5,671,399 · App. 08/498,687
Method for hierarchic logic verification of VLSI circuits
Inventor:
Wolfgang Meier
Patented Case
View Patent ↗
Granted: Sep 23, 1997
Filed: Jul 3, 1995
Inventor
Wolfgang Meier
Assignee (at issue)
Siemens Aktiengesellschaft
This patent predates the USPTO's electronic file wrapper — prosecution documents from this era exist only in the Patent Office's paper records. A certified copy of the file history can be ordered from the USPTO's paper archives.