IP Library › Granted Patent US 5,672,995
Granted Patent Utility
US 5,672,995 · App. 08/340,343

High speed mis-type intergrated circuit with self-regulated back bias

Inventors: Junji Hirase, Hironori Akamatsu, Susumu Akamatsu, Takashi Hori
Patented Case View Patent ↗
Granted: Sep 30, 1997 Filed: Nov 14, 1994
Inventors
Junji Hirase
Hironori Akamatsu
Susumu Akamatsu
Takashi Hori
Assignee (at issue)
SUMITOMO ELECTRIC INDUSTRIES, LTD.

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Quick Facts
Patent No.
US 5,672,995
App. No.
08/340,343
Filed
1994-11-14
Granted
1997-09-30
Kind
A