IP Library › Granted Patent US 5,678,020
Granted Patent Utility
US 5,678,020 · App. 08/757,959

Memory subsystem wherein a single processor chip controls multiple cache memory chips

Inventors: Gurbir Singh, Konrad K. Lai
Patented Case View Patent ↗
Granted: Oct 14, 1997 Filed: Nov 25, 1996
Inventors
Gurbir Singh
Konrad K. Lai
Assignee (at issue)
Intel Corporation

This patent predates the USPTO's electronic file wrapper — prosecution documents from this era exist only in the Patent Office's paper records. A certified copy of the file history can be ordered from the USPTO's paper archives.

Order Certified Copies
Most orders are placed with the USPTO same day — all within 24 business hours.
Order via The Patent Place →
Pre-filled with this patent's details
Quick Facts
Patent No.
US 5,678,020
App. No.
08/757,959
Filed
1996-11-25
Granted
1997-10-14
Kind
A