Granted Patent
Utility
US 5,687,340 · App. 08/442,544
Reduced area floating point processor control logic utilizing a decoder between a control unit and the FPU
Inventors:
Jon L Ashburn, Theodore G. Rossin
Patented Case
View Patent ↗
Granted: Nov 11, 1997
Filed: May 16, 1995
Inventors
Jon L Ashburn
Theodore G. Rossin
Assignee (at issue)
Hewlett-Packard Company, L.P.
This patent predates the USPTO's electronic file wrapper — prosecution documents from this era exist only in the Patent Office's paper records. A certified copy of the file history can be ordered from the USPTO's paper archives.