IP Library › Granted Patent US 5,688,722
Granted Patent Utility
US 5,688,722 · App. 07/899,409

CMOS integrated circuit with reduced susceptibility to PMOS punchthrough

Inventor: Thomas E. Harrington, III
Patented Case View Patent ↗
Granted: Nov 18, 1997 Filed: Jun 16, 1992
Inventor
Thomas E. Harrington, III
Assignee (at issue)
Dallas Semiconductor Corporation

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Quick Facts
Patent No.
US 5,688,722
App. No.
07/899,409
Filed
1992-06-16
Granted
1997-11-18
Kind
A