Granted Patent
Utility
US 5,696,452 · App. 08/512,323
Arrangement and method for improving room-temperature testability of CMOS integrated circuits optimized for cryogenic temperature operation
Inventors:
Donald F. Hemmenway, John T. Gasner, William R. Young
Patented Case
View Patent ↗
Granted: Dec 9, 1997
Filed: Aug 8, 1995
Inventors
Donald F. Hemmenway
John T. Gasner
William R. Young
Assignee (at issue)
HARRIS CORPORATION
This patent predates the USPTO's electronic file wrapper — prosecution documents from this era exist only in the Patent Office's paper records. A certified copy of the file history can be ordered from the USPTO's paper archives.