Granted Patent
Utility
US 5,737,233 · App. 08/583,296
VLSI circuit layout method based on spreading functions and simulated annealing heuristics to minimize area
Inventor:
Satish B. Rao
Patented Case
View Patent ↗
Granted: Apr 7, 1998
Filed: Jan 5, 1996
Inventor
Satish B. Rao
Assignee (at issue)
NEC Research Institute, Inc.
This patent predates the USPTO's electronic file wrapper — prosecution documents from this era exist only in the Patent Office's paper records. A certified copy of the file history can be ordered from the USPTO's paper archives.