Granted Patent
Utility
US 5,764,528 · App. 08/670,128
Delay optimizing method in logic circuit designing
Inventor:
Atsushi Nakamura
Patented Case
View Patent ↗
Granted: Jun 9, 1998
Filed: Jun 25, 1996
Inventor
Atsushi Nakamura
Assignee (at issue)
NEC CORPORATION
This patent predates the USPTO's electronic file wrapper — prosecution documents from this era exist only in the Patent Office's paper records. A certified copy of the file history can be ordered from the USPTO's paper archives.