Granted Patent
Utility
US 5,767,713 · App. 08/569,682
Phase locked loop having integration gain reduction
Inventor:
Bertrand J. Williams
Patented Case
View Patent ↗
Granted: Jun 16, 1998
Filed: Dec 8, 1995
Inventor
Bertrand J. Williams
Assignee (at issue)
Cypress Semiconductor Corporation
This patent predates the USPTO's electronic file wrapper — prosecution documents from this era exist only in the Patent Office's paper records. A certified copy of the file history can be ordered from the USPTO's paper archives.