IP Library Granted Patent US 5,778,432
Granted Patent Utility
US 5,778,432 · App. 08/674,050

Method and apparatus for performing different cache replacement algorithms for flush and non-flush operations in response to a cache flush control bit register

Inventors: Lawrence H. Rubin, Paul A. Reed
Patented Case View Patent ↗
Granted: Jul 7, 1998 Filed: Jul 1, 1996
Inventors
Lawrence H. Rubin
Paul A. Reed
Assignee (at issue)
Motorola, Inc.

This patent predates the USPTO's electronic file wrapper — prosecution documents from this era exist only in the Patent Office's paper records. A certified copy of the file history can be ordered from the USPTO's paper archives.

Order Certified Copies
Most orders are placed with the USPTO same day — all within 24 business hours.
Order via The Patent Place →
Pre-filled with this patent's details
Quick Facts
Patent No.
US 5,778,432
App. No.
08/674,050
Filed
1996-07-01
Granted
1998-07-07
Kind
A