Granted Patent
Utility
US 5,801,983 · App. 08/590,516
Semiconductor memory device having memory cells designed to offset bit line parasitic capacitance
Inventor:
Takanori Saeki
Patented Case
View Patent ↗
Granted: Sep 1, 1998
Filed: Jan 29, 1996
Inventor
Takanori Saeki
Assignee (at issue)
NEC CORPORATION
This patent predates the USPTO's electronic file wrapper — prosecution documents from this era exist only in the Patent Office's paper records. A certified copy of the file history can be ordered from the USPTO's paper archives.