Granted Patent
Utility
US 5,870,574 · App. 08/686,363
System and method for fetching multiple groups of instructions from an instruction cache in a RISC processor system for execution during separate cycles
Inventors:
Andre Kowalczyk, Givargis G. Kaldani
Patented Case
View Patent ↗
Granted: Feb 9, 1999
Filed: Jul 24, 1996
Inventors
Andre Kowalczyk
Givargis G. Kaldani
Assignee (at issue)
Silicon Graphics, Inc.
This patent predates the USPTO's electronic file wrapper — prosecution documents from this era exist only in the Patent Office's paper records. A certified copy of the file history can be ordered from the USPTO's paper archives.