Circuits and methods for read-enabling memory devices synchronously with the reaching of the minimum functionality conditions of the memory cells and reading circuits, particularly for non-volatile memories

Granted: Mar 2, 1999 Filed: Apr 24, 1997

This patent predates the USPTO's electronic file wrapper — prosecution documents from this era exist only in the Patent Office's paper records. A certified copy of the file history can be ordered from the USPTO's paper archives.