Granted Patent
Utility
US 5,883,808 · App. 08/791,755
Logic circuit optimization apparatus and its method
Inventor:
Masamichi Kawarabayashi
Patented Case
View Patent ↗
Granted: Mar 16, 1999
Filed: Jan 29, 1997
Inventor
Masamichi Kawarabayashi
Assignee (at issue)
NEC CORPORATION
This patent predates the USPTO's electronic file wrapper — prosecution documents from this era exist only in the Patent Office's paper records. A certified copy of the file history can be ordered from the USPTO's paper archives.