Granted Patent
Utility
US 5,901,063 · App. 08/804,524
System and method for extracting parasitic impedance from an integrated circuit layout
Inventors:
Keh-Jeng Chang, Douglas Francis Kaufman, Martin G. Walker
Patented Case
View Patent ↗
Granted: May 4, 1999
Filed: Feb 21, 1997
Inventors
Keh-Jeng Chang
Douglas Francis Kaufman
Martin G. Walker
Assignee (at issue)
Frequency Technology, Inc.
This patent predates the USPTO's electronic file wrapper — prosecution documents from this era exist only in the Patent Office's paper records. A certified copy of the file history can be ordered from the USPTO's paper archives.