Granted Patent
Utility
US 5,936,271 · App. 08/340,500
Unit cell layout and transfer gate design for high density DRAMs having a trench capacitor with signal electrode composed of three differently doped polysilicon layers
Inventors:
Johann Alsmeier, Martin Gall
Patented Case
View Patent ↗
Granted: Aug 10, 1999
Filed: Nov 15, 1994
Inventors
Johann Alsmeier
Martin Gall
Assignee (at issue)
Siemens Aktiengesellschaft
This patent predates the USPTO's electronic file wrapper — prosecution documents from this era exist only in the Patent Office's paper records. A certified copy of the file history can be ordered from the USPTO's paper archives.