IP Library › Granted Patent US 5,960,256
Granted Patent Utility
US 5,960,256 · App. 08/962,399

Wafer layout of semiconductor device and manufacturing method thereof

Inventors: Keiji Sato, Yutaka Saito
Patented Case View Patent ↗
Granted: Sep 28, 1999 Filed: Oct 31, 1997
Inventors
Keiji Sato
Yutaka Saito
Assignee (at issue)
SII R&D Center Inc.

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Quick Facts
Patent No.
US 5,960,256
App. No.
08/962,399
Filed
1997-10-31
Granted
1999-09-28
Kind
A