Granted Patent
Utility
US 5,966,037 · App. 08/795,363
Method for manufacturing an integrated circuit with programmable non-overlapping-clock-edge capability
Inventors:
Ho Dai Truong, Chong Ming Lin
Patented Case
View Patent ↗
Granted: Oct 12, 1999
Filed: Feb 4, 1997
Inventors
Ho Dai Truong
Chong Ming Lin
Assignee (at issue)
SEIKO EPSON CORPORATION, Tokyo, JAPAN;
This patent predates the USPTO's electronic file wrapper — prosecution documents from this era exist only in the Patent Office's paper records. A certified copy of the file history can be ordered from the USPTO's paper archives.