Granted Patent
Utility
US 5,973,397 · App. 08/955,929
Semiconductor device and fabrication method which advantageously combine wire bonding and tab techniques to increase integrated circuit I/O pad density
Inventors:
Qwai H. Low, Chok J. Chia, Seng-Sooi Lim
Patented Case
View Patent ↗
Granted: Oct 26, 1999
Filed: Oct 22, 1997
Inventors
Qwai H. Low
Chok J. Chia
Seng-Sooi Lim
Assignee (at issue)
LSI Logic Corporation
This patent predates the USPTO's electronic file wrapper — prosecution documents from this era exist only in the Patent Office's paper records. A certified copy of the file history can be ordered from the USPTO's paper archives.