Granted Patent
Utility
US 5,985,705 · App. 09/107,767
Low threshold voltage MOS transistor and method of manufacture
Inventor:
John J. Seliskar
Patented Case
View Patent ↗
Granted: Nov 16, 1999
Filed: Jun 30, 1998
Inventor
John J. Seliskar
Assignee (at issue)
LSI Logic Corporation
This patent predates the USPTO's electronic file wrapper — prosecution documents from this era exist only in the Patent Office's paper records. A certified copy of the file history can be ordered from the USPTO's paper archives.