Granted Patent
Utility
US 6,002,277 · App. 09/055,561
Sample-and-hold circuit having reduced parasitic diode effects and related methods
Inventors:
Salomon Vulih, Donald R. Preslar, Thomas A. Jochum
Patented Case
View Patent ↗
Granted: Dec 14, 1999
Filed: Apr 6, 1998
Inventors
Salomon Vulih
Donald R. Preslar
Thomas A. Jochum
Assignee (at issue)
Intersil Corporation
This patent predates the USPTO's electronic file wrapper — prosecution documents from this era exist only in the Patent Office's paper records. A certified copy of the file history can be ordered from the USPTO's paper archives.