Granted Patent
Utility
US 6,021,075 · App. 09/161,217
Semiconductor memory circuit having shift redundancy circuits
Inventor:
Yoshinori Ueno
Patented Case
View Patent ↗
Granted: Feb 1, 2000
Filed: Sep 28, 1998
Inventor
Yoshinori Ueno
Assignee (at issue)
NEC CORPORATION
This patent predates the USPTO's electronic file wrapper — prosecution documents from this era exist only in the Patent Office's paper records. A certified copy of the file history can be ordered from the USPTO's paper archives.