Granted Patent
Utility
US 6,028,995 · App. 09/052,914
Method of determining delay in logic cell models
Inventors:
Mark W. Jetton, Anura P. Jayasumana
Patented Case
View Patent ↗
Granted: Feb 22, 2000
Filed: Mar 31, 1998
Inventors
Mark W. Jetton
Anura P. Jayasumana
Assignee (at issue)
LSI Logic Corporation
This patent predates the USPTO's electronic file wrapper — prosecution documents from this era exist only in the Patent Office's paper records. A certified copy of the file history can be ordered from the USPTO's paper archives.