Granted Patent
Utility
US 6,046,060 · App. 09/062,530
Method of making a high planarity, low CTE base for semiconductor reliability screening
Inventor:
John J. Budnaitis
Patented Case
View Patent ↗
Granted: Apr 4, 2000
Filed: Apr 17, 1998
Inventor
John J. Budnaitis
Assignee (at issue)
W. L. Gore & Associates, Inc.
This patent predates the USPTO's electronic file wrapper — prosecution documents from this era exist only in the Patent Office's paper records. A certified copy of the file history can be ordered from the USPTO's paper archives.