Granted Patent
Utility
US 6,060,784 · App. 08/768,577
Interconnection layer structure in a semiconductor integrated circuit device having macro cell regions
Inventor:
Noriaki Oda
Patented Case
View Patent ↗
Granted: May 9, 2000
Filed: Dec 18, 1996
Inventor
Noriaki Oda
Assignee (at issue)
NEC CORPORATION
This patent predates the USPTO's electronic file wrapper — prosecution documents from this era exist only in the Patent Office's paper records. A certified copy of the file history can be ordered from the USPTO's paper archives.