Granted Patent
Utility
US 6,060,895 · App. 09/062,907
Wafer level dielectric test structure and related method for accelerated endurance testing
Inventors:
Sik-Han Soh, Max C. Kuo
Patented Case
View Patent ↗
Granted: May 9, 2000
Filed: Apr 20, 1998
Inventors
Sik-Han Soh
Max C. Kuo
Assignee (at issue)
FAIRCHILD SEMICONDUCTOR CORPORATION
This patent predates the USPTO's electronic file wrapper — prosecution documents from this era exist only in the Patent Office's paper records. A certified copy of the file history can be ordered from the USPTO's paper archives.