Granted Patent
Utility
US 6,066,876 · App. 09/065,173
Integrated circuit arrangement having at least one MOS transistor manufactured by use of a planar transistor layout
Inventors:
Lothar Risch, Wolfgang Roesner, Thomas Aeugle, Wolfgang Krautschneider
Patented Case
View Patent ↗
Granted: May 23, 2000
Filed: Apr 23, 1998
Inventors
Lothar Risch
Wolfgang Roesner
Thomas Aeugle
Wolfgang Krautschneider
Assignee (at issue)
Siemens Aktiengesellschaft
This patent predates the USPTO's electronic file wrapper — prosecution documents from this era exist only in the Patent Office's paper records. A certified copy of the file history can be ordered from the USPTO's paper archives.