Granted Patent
Utility
US 6,084,436 · App. 08/957,134
Multi-input semiconductor logic device with mask pattern for reduced parasitic capacitance
Inventor:
Toshio Komuro
Patented Case
View Patent ↗
Granted: Jul 4, 2000
Filed: Oct 24, 1997
Inventor
Toshio Komuro
Assignee (at issue)
NEC CORPORATION
This patent predates the USPTO's electronic file wrapper — prosecution documents from this era exist only in the Patent Office's paper records. A certified copy of the file history can be ordered from the USPTO's paper archives.