Granted Patent
Utility
US 6,090,149 · App. 09/026,297
System and method for detecting floating nodes within a simulated integrated circuit
Inventors:
Vijayakumaran V. Nair, Ronald D. Holifield
Patented Case
View Patent ↗
Granted: Jul 18, 2000
Filed: Feb 19, 1998
Inventors
Vijayakumaran V. Nair
Ronald D. Holifield
Assignee (at issue)
Advanced Micro Devices, Inc.
This patent predates the USPTO's electronic file wrapper — prosecution documents from this era exist only in the Patent Office's paper records. A certified copy of the file history can be ordered from the USPTO's paper archives.