Granted Patent
Utility
US 6,091,090 · App. 08/933,552
Power and signal routing technique for gate array design
Inventor:
Tushar R. Gheewala
Patented Case
View Patent ↗
Granted: Jul 18, 2000
Filed: Sep 19, 1997
Inventor
Tushar R. Gheewala
Assignee (at issue)
In-Chip Systems, Inc.
This patent predates the USPTO's electronic file wrapper — prosecution documents from this era exist only in the Patent Office's paper records. A certified copy of the file history can be ordered from the USPTO's paper archives.