Granted Patent
Utility
US 6,131,168 · App. 09/271,551
System and method for reducing phase error in clocks produced by a delay locked loop
Inventor:
Richard A. Krzyzkowski
Patented Case
View Patent ↗
Granted: Oct 10, 2000
Filed: Mar 18, 1999
Inventor
Richard A. Krzyzkowski
Assignee (at issue)
Agilent Technologies, Inc.
This patent predates the USPTO's electronic file wrapper — prosecution documents from this era exist only in the Patent Office's paper records. A certified copy of the file history can be ordered from the USPTO's paper archives.