Granted Patent
Utility
US 6,146,912 · App. 09/309,945
Method for parallel alignment of a chip to substrate
Inventors:
Thomas S. Tighe, Gershon Akerling
Patented Case
View Patent ↗
Granted: Nov 14, 2000
Filed: May 11, 1999
Inventors
Thomas S. Tighe
Gershon Akerling
Assignee (at issue)
TRW Limited
This patent predates the USPTO's electronic file wrapper — prosecution documents from this era exist only in the Patent Office's paper records. A certified copy of the file history can be ordered from the USPTO's paper archives.