Granted Patent
Utility
US 6,166,991 · App. 09/433,822
Circuit, architecture and method for reducing power consumption in a synchronous integrated circuit
Inventor:
Cathal G. Phelan
Patented Case
View Patent ↗
Granted: Dec 26, 2000
Filed: Nov 3, 1999
Inventor
Cathal G. Phelan
Assignee (at issue)
Cypress Semiconductor Corporation
This patent predates the USPTO's electronic file wrapper — prosecution documents from this era exist only in the Patent Office's paper records. A certified copy of the file history can be ordered from the USPTO's paper archives.