Granted Patent
Utility
US 6,198,682 · App. 09/329,975
Hierarchical dynamic memory array architecture using read amplifiers separate from bit line sense amplifiers
Inventor:
Robert J. Proebsting
Patented Case
View Patent ↗
Granted: Mar 6, 2001
Filed: Jun 10, 1999
Inventor
Robert J. Proebsting
Assignee (at issue)
Integrated Device Technology, Inc.
This patent predates the USPTO's electronic file wrapper — prosecution documents from this era exist only in the Patent Office's paper records. A certified copy of the file history can be ordered from the USPTO's paper archives.