Granted Patent
Utility
US 6,205,461 · App. 09/157,090
Floating point arithmetic logic unit leading zero count using fast approximate rounding
Inventor:
Sanjay Mansingh
Patented Case
View Patent ↗
Granted: Mar 20, 2001
Filed: Sep 18, 1998
Inventor
Sanjay Mansingh
Assignee (at issue)
ATI International SRL
This patent predates the USPTO's electronic file wrapper — prosecution documents from this era exist only in the Patent Office's paper records. A certified copy of the file history can be ordered from the USPTO's paper archives.