IP Library Granted Patent US 6,209,052
Granted Patent Utility
US 6,209,052 · App. 09/164,194

System and method for suppressing processor cycles to memory until after a peripheral device write cycle is acknowledged by the memory arbiter

Inventors: Kenneth T. Chin, Clarence K. Coffee, Michael J. Collins, Jerome J. Johnson, Phillip M. Jones, Robert A. Lester, Gary J. Piccirillo
Patented Case View Patent ↗
Granted: Mar 27, 2001 Filed: Sep 30, 1998
Inventors
Kenneth T. Chin
Clarence K. Coffee
Michael J. Collins
Jerome J. Johnson
Phillip M. Jones
Robert A. Lester
Gary J. Piccirillo
Assignee (at issue)
Compaq Computer Corporation

This patent predates the USPTO's electronic file wrapper — prosecution documents from this era exist only in the Patent Office's paper records. A certified copy of the file history can be ordered from the USPTO's paper archives.

Order Certified Copies
Most orders are placed with the USPTO same day — all within 24 business hours.
Order via The Patent Place →
Pre-filled with this patent's details
Quick Facts
Patent No.
US 6,209,052
App. No.
09/164,194
Filed
1998-09-30
Granted
2001-03-27
Kind
A