IP Library Granted Patent US 6,236,618
Granted Patent Utility
US 6,236,618 · App. 09/542,033

Centrally decoded divided wordline (DWL) memory architecture

Inventor: Richard S. Roy
Patented Case View Patent ↗
Granted: May 22, 2001 Filed: Apr 3, 2000
Inventor
Richard S. Roy
Assignee (at issue)
Virage Logic Corporation

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Quick Facts
Patent No.
US 6,236,618
App. No.
09/542,033
Filed
2000-04-03
Granted
2001-05-22
Kind
A