Granted Patent
Utility
US 6,239,042 · App. 08/987,454
Process for realizing an intermediate dielectric layer for enhancing the planarity in semiconductor electronic devices
Inventors:
Patrizia Sonego, Maurizio Bacchetta
Patented Case
View Patent ↗
Granted: May 29, 2001
Filed: Dec 9, 1997
Inventors
Patrizia Sonego
Maurizio Bacchetta
Assignee (at issue)
SGS-Thomson Microelectronics S.A.
This patent predates the USPTO's electronic file wrapper — prosecution documents from this era exist only in the Patent Office's paper records. A certified copy of the file history can be ordered from the USPTO's paper archives.