IP Library › Granted Patent US 6,289,413
Granted Patent Utility
US 6,289,413 · App. 09/360,373

Cached synchronous DRAM architecture having a mode register programmable cache policy

Inventors: Jim L. Rogers, Steven W. Tomashot, David Bondurant, Oscar Frederick Jones, Jr., Kenneth J. Mobley
Patented Case View Patent ↗
Granted: Sep 11, 2001 Filed: Oct 15, 1999
Inventors
Jim L. Rogers
Steven W. Tomashot
David Bondurant
Oscar Frederick Jones, Jr.
Kenneth J. Mobley
Assignee (at issue)
International Business Machines Corporation

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Quick Facts
Patent No.
US 6,289,413
App. No.
09/360,373
Filed
1999-10-15
Granted
2001-09-11
Kind
A