Granted Patent
Utility
US 6,310,367 · App. 09/510,239
MOS transistor having a tensile-strained SI layer and a compressive-strained SI-GE layer
Inventors:
Atsushi Yagishita, Kouji Matsuo
Patented Case
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Granted: Oct 30, 2001
Filed: Feb 22, 2000
Inventors
Atsushi Yagishita
Kouji Matsuo
Assignee (at issue)
Kabushiki Kaisha Toshiba
This patent predates the USPTO's electronic file wrapper — prosecution documents from this era exist only in the Patent Office's paper records. A certified copy of the file history can be ordered from the USPTO's paper archives.