Granted Patent
Utility
US 6,335,875 · App. 09/769,390
Memory circuit/logic circuit integrated device capable of reducing term of works
Inventor:
Tsukasa Ooishi
Patented Case
View Patent ↗
Granted: Jan 1, 2002
Filed: Jan 26, 2001
Inventor
Tsukasa Ooishi
Assignee (at issue)
MITSUBISHI ELECTRIC CORPORATION
This patent predates the USPTO's electronic file wrapper — prosecution documents from this era exist only in the Patent Office's paper records. A certified copy of the file history can be ordered from the USPTO's paper archives.