Test circuits for testing inter-device FPGA links including a shift register configured from FPGA elements to form a shift block through said inter-device FPGA links

Granted: Feb 12, 2002 Filed: Oct 9, 1998

This patent predates the USPTO's electronic file wrapper — prosecution documents from this era exist only in the Patent Office's paper records. A certified copy of the file history can be ordered from the USPTO's paper archives.