Granted Patent
Utility
US 6,388,928 · App. 09/852,603
Method and system for reduction of test time for analog chip manufacturing
Inventors:
Theodore M. Myers, Richard V. Orlando
Patented Case
View Patent ↗
Granted: May 14, 2002
Filed: May 10, 2001
Inventors
Theodore M. Myers
Richard V. Orlando
Assignee (at issue)
Summit Microelectronics, Inc.
This patent predates the USPTO's electronic file wrapper — prosecution documents from this era exist only in the Patent Office's paper records. A certified copy of the file history can be ordered from the USPTO's paper archives.