Granted Patent
Utility
US 6,396,331 · App. 09/686,514
Mechanism for minimizing undesirable effects of parasitic components in integrated circuits
Inventor:
Leonel Ernesto Enriquez
Patented Case
View Patent ↗
Granted: May 28, 2002
Filed: Oct 11, 2000
Inventor
Leonel Ernesto Enriquez
Assignee (at issue)
Intersil Americas LLC
This patent predates the USPTO's electronic file wrapper — prosecution documents from this era exist only in the Patent Office's paper records. A certified copy of the file history can be ordered from the USPTO's paper archives.