Granted Patent
Utility
US 6,403,978 · App. 09/261,280
Test pattern for measuring variations of critical dimensions of wiring patterns formed in the fabrication of semiconductor devices
Inventor:
Jong-Cheol Kim
Patented Case
View Patent ↗
Granted: Jun 11, 2002
Filed: Mar 2, 1999
Inventor
Jong-Cheol Kim
Assignee (at issue)
Citicorp USA, Inc.
This patent predates the USPTO's electronic file wrapper — prosecution documents from this era exist only in the Patent Office's paper records. A certified copy of the file history can be ordered from the USPTO's paper archives.