IP Library › Granted Patent US 6,463,572
Granted Patent Utility
US 6,463,572 · App. 09/871,129

IC timing analysis with known false paths

Inventors: Ivan Pavisic, Pedja Raspopovic, Aiguo Lu
Patented Case View Patent ↗
Granted: Oct 8, 2002 Filed: May 31, 2001
Inventors
Ivan Pavisic
Pedja Raspopovic
Aiguo Lu
Assignee (at issue)
LSI Logic Corporation

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Quick Facts
Patent No.
US 6,463,572
App. No.
09/871,129
Filed
2001-05-31
Granted
2002-10-08
Kind
B1