Granted Patent
Utility
US 6,473,356 · App. 10/002,568
Low power read circuitry for a memory circuit based on charge redistribution between bitlines and sense amplifier
Inventor:
Jaroslav Raszka
Patented Case
View Patent ↗
Granted: Oct 29, 2002
Filed: Nov 1, 2001
Inventor
Jaroslav Raszka
Assignee (at issue)
Virage Logic Corporation
This patent predates the USPTO's electronic file wrapper — prosecution documents from this era exist only in the Patent Office's paper records. A certified copy of the file history can be ordered from the USPTO's paper archives.