Granted Patent
Utility
US 6,477,075 · App. 10/003,255
Memory circuit/logic circuit integrated device capable of reducing term of works
Inventor:
Tsukasa Ooishi
Patented Case
View Patent ↗
Granted: Nov 5, 2002
Filed: Dec 6, 2001
Inventor
Tsukasa Ooishi
Assignee (at issue)
MITSUBISHI ELECTRIC CORPORATION
This patent predates the USPTO's electronic file wrapper — prosecution documents from this era exist only in the Patent Office's paper records. A certified copy of the file history can be ordered from the USPTO's paper archives.