Granted Patent
Utility
US 6,493,836 · App. 09/726,738
Method and apparatus for scheduling and using memory calibrations to reduce memory errors in high speed memory devices
Inventors:
Sompong Paul Olarig, John E. Jenne
Patented Case
View Patent ↗
Granted: Dec 10, 2002
Filed: Nov 30, 2000
Inventors
Sompong Paul Olarig
John E. Jenne
Assignee (at issue)
COMPAQ Information Technologies Group, L.P.
This patent predates the USPTO's electronic file wrapper — prosecution documents from this era exist only in the Patent Office's paper records. A certified copy of the file history can be ordered from the USPTO's paper archives.