Granted Patent
Utility
US 6,501,673 · App. 09/881,661
Circuit arrangement for the lowering of the threshold voltage of a diode configured transistor
Inventors:
Carlo Lisi, Lorenzo Bedarida, Antonino Geraci, Vincenzo Dima
Patented Case
View Patent ↗
Granted: Dec 31, 2002
Filed: Jun 13, 2001
Inventors
Carlo Lisi
Lorenzo Bedarida
Antonino Geraci
Vincenzo Dima
Assignee (at issue)
STMICROELECTRONICS S.r.l.
This patent predates the USPTO's electronic file wrapper — prosecution documents from this era exist only in the Patent Office's paper records. A certified copy of the file history can be ordered from the USPTO's paper archives.